Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell (e.g., floating gate) that allows for high memory densities, high reliability, and low power consumption. Changes in threshold voltage of the cells, through programming of charge storage trapping layers or other physical phenomena, determine the data state of each cell. Common uses for flash memory and other non-volatile memory include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, appliances, vehicles, wireless devices, mobile telephones, and removable memory modules, and the uses for non-volatile memory continue to expand.
Flash memory typically utilizes one of two basic architectures known as NOR Flash and NAND Flash. The designation is derived from the logic used to read the devices. FIG. 1 illustrates a typical NAND type flash memory array architecture 100 wherein the floating gate memory cells 101 of the memory array are logically arranged in a matrix of rows and columns. The memory cells 101 of the array are shown arranged together in strings, typically of 8, 16, 32, or more each, where the memory cells in the string are connected together in series, source to drain, between a common source line 120 and a data line 122, often referred to as a bit line. The array is then accessed by a row decoder activating a row of floating gate memory cells (e.g., 132-138) by selecting a particular access line (e.g., 130), often referred to as a word line, connected to their gates. In addition, bit lines BL0-BL3 122-128 can also be driven high or low depending on the current operation being performed. As is known to those skilled in the art, the number of word lines and bit lines might be much greater than those shown in FIG. 1.
Bit lines BL0-BL3 122-128 are shown coupled to sensing devices (e.g., sense amplifiers) 140-146 that detect the state of each cell by sensing current on a particular bit line 122-128. The word lines WL7-WL0 104-116 and 130 select the individual memory cells 101 in the series strings to be written to or read from and operate the remaining memory cells in each series string in a pass through mode. Each series string of memory cells is coupled to a source line 120 by a source select gate 150 and to an individual bit line BL0 122 by a drain select gate 148, for example. The source select gates, such as 150, are controlled by a source select gate control line SG(S) 118 coupled to their control gates. The drain select gates, such as 148, are controlled by a drain select gate control line SG(D) 102.
As the performance and complexity of electronic systems increase, the requirement for additional memory in systems also increases. However, in order to continue to reduce the costs of the system, it is desirable to keep the parts count low. This can be accomplished by increasing the memory density of an integrated circuit by using such technologies as multilevel cells (MLC). For example, MLC NAND flash memory is a cost effective non-volatile memory.
Multilevel memory cells assign a data state (e.g., as represented by a bit pattern) to a specific range of threshold voltages (Vt) stored on the memory cell. Single level memory cells (SLC) permit the storage of a single bit of data on each memory cell. Meanwhile, MLC technology permits the storage of two or more binary digits (e.g., bits) per cell (e.g., 2, 4, 8, 16 bits), depending on the quantity of threshold voltage ranges assigned to the cell and the stability of the assigned threshold voltage ranges during the lifetime operation of the memory cell. The number of threshold voltage ranges (e.g., levels) used to represent a bit pattern comprised of N-bits is 2N. For example, one bit may be represented by two levels, two bits by four levels, three bits by eight levels, etc. A common naming convention is to refer to SLC memory as MLC (two level) memory as SLC memory utilizes two levels in order to store one bit of data as represented by a 0 or a 1, for example. MLC memory configured to store two bits of data can be represented by MLC (four level), three bits of data by MLC (eight level), etc. An MLC (four level) memory cell is typically referred to as a lower density memory cell than an MLC (eight level) memory due to the lower number of bits stored per memory cell, for example. SLC (e.g., MLC (two level)) is typically referred to as a lower density memory than MLC (four level) memory and so on.
FIG. 2 illustrates an example of Vt distribution 200 for a MLC (four-level) memory cell. For example, a cell may be assigned a Vt that falls within one of four different voltage ranges 202-208 of 200 mV, each being used to represent a data state corresponding to a bit pattern comprised of two bits. Typically, a dead space 210 (which is sometimes referred to as a margin) of 0.2V to 0.4V is maintained between each range to keep the ranges from overlapping. As one example, if the voltage stored on the cell is within the first of the four Vt ranges 202, the cell in this case is storing a logical ‘11’ state and is typically considered the erased state of the cell. If the voltage is within the second of the four Vt ranges 204, the cell in this case is storing a logical ‘10’ state. A voltage in the third range 206 of the four Vt ranges would indicate that the cell in this case is storing a logical ‘00’ state. Finally, a Vt residing in the fourth Vt range 208 indicates that a logical ‘01’ state is stored in the cell.
During a typical programming operation of memory cells (e.g. a block) with user data, some additional memory cells are programmed with a known reference value (e.g., reference level.) Over time, the threshold voltages programmed in memory cells, including the reference cells, may drift by some amount. Thus, due to their proximity it is assumed that the amount of drift observed in a reference cell is similar to the amount of drift in a memory cell storing user data. Thus, a determination of how much drift has occurred can be made by comparing the known value programmed into the reference cell with the level actually read from the reference cell. Typically these reference memory cells are arranged such that a complete string comprises memory cells which are all programmed to the same reference level. Additional strings comprise memory cells all programmed to a second reference level, etc.
However, one issue with utilizing this method of determining drift in reference cells is that the resistance of a series string of memory cells varies in response to the programmed pattern (e.g., levels) of the memory cells above and below a target cell in a series string. A change in resistance causes the bit line discharge rate to change, resulting in an error being introduced. This error mechanism is typically referred to as back pattern effect. In the case of strings of reference cells, all of the memory cells above and below each reference cell are programmed to the same level. This is in contrast to strings of memory cells storing user data in that, statistically speaking, the memory cells above and below a particular memory cell (e.g., target cell) store user data that is random. Thus, the user data memory cells experience a different back pattern effect than the reference cells would experience and thereby additional errors between reference and data cells of the array are introduced.
For the reasons stated above, and for other reasons which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art to manage this back pattern and other effects in reference cells of a memory device.